1. Field of the Invention
The present invention relates generally to low capacitance integrated circuits formed within and upon semiconductor substrates. More particularly, the present invention relates to low input capacitance input/output integrated circuits formed within and upon semiconductor substrates.
2. Description of Related Art
Integrated circuits are typically fabricated from semiconductor substrates within and upon whose surfaces are formed transistors, resistors, diodes, capacitors and other electrical circuit elements. These electrical circuit elements are connected internally and externally to the semiconductor substrate within and upon which they are formed through conductor metallization layers which are separated by insulating layers.
Electrical circuit elements may be arranged and connected within and upon semiconductor substrates in various fashions to accomplish diverse electrical functions. For example, within digital integrated circuit technology electrical circuit elements may be arranged to: (1) form charge storage locations for digital data input, and (2) form operational integrated circuits which perform mathematical functions upon digital data stored within those charge storage locations.
In order to effectively transfer electrical signals to charge storage locations or operational integrated circuits formed within and upon a semiconductor substrate it is common practice in the art to design and fabricate within and upon the semiconductor substrate input/output integrated circuits which provide electrical pathways through which electrical signals external to the semiconductor substrate must travel in order to reach the charge storage locations or operational integrated circuits within and upon the semiconductor substrate. These input/output integrated circuits are often designed and fabricated with Electro-Static Discharge (ESD) protection integrated sub-circuits within their constructions. The Electro-Static Discharge (ESD) protection integrated sub-circuits are designed to limit damage which might otherwise occur to the charge storage locations or operational integrated circuits through conduction and dissipation of unpredictable and uncontrollable Electro-Static Discharges (ESDs).
The Electro-Static Discharge (ESD) protection integrated sub-circuits and the input/output integrated circuits within which they reside are typically formed between the input/output terminal of the completed integrated circuit upon the semiconductor substrate, and the charge storage location or operational integrated circuit desired to be protected from Electro-Static Discharges (ESDs). The Electro-Static Discharge (ESD) protection integrated sub-circuits are typically fabricated from electrical circuit elements similar to the electrical circuit elements employed in forming the charge storage locations or operational integrated circuits which they protect. Typically, these electrical circuit elements will include transistors and resistors as are common in the art.
While Electro-Static Discharge (ESD) protection integrated sub-circuits and the input/output integrated circuits within which they reside usually provide the desired level of protection and access to the charge storage locations and operational integrated circuits to which they are connected, Electro-Static Discharge (ESD) protection integrated sub-circuits and input/output integrated circuits within which they reside are often not without negative characteristics. Specifically, input/output integrated circuits and Electro-Static Discharge (ESD) protection integrated sub-circuits within those input/output integrated circuits often add substantial input capacitance to the charge storage locations and operational integrated circuits to which they are connected. This input capacitance often derives from capacitances of junctions within electrical circuit elements from which are formed input/output integrated circuits and Electro-Static Discharge (ESD) protection integrated sub-circuits. Substantial input capacitances are often undesirable in advanced integrated circuits since electrical circuit capacitances, in general, contribute to delays in integrated circuit switching speeds.
It is thus an object of the present invention to provide an Electro-Static Discharge (ESD) protection integrated sub-circuit within an input/output integrated circuit upon a semiconductor substrate, which Electro-Static Discharge (ESD) protection integrated sub-circuit and input/output integrated circuit have lower input capacitances in comparison with Electro-Static Discharge (ESD) protection integrated sub-circuits and input/output integrated circuits conventional to the art, while simultaneously maintaining the Electro-Static Discharge (ESD) properties of the Electro-Static Discharge (ESD) protection integrated sub-circuit within the input/output integrated circuit.